In practice, the formation of a microelectronics component implies various steps involving layers of a few nanometers to a few microns, or even of a tens of microns, in which all or part of the components are formed. The material most used in this field is silicon, but other materials are also used, such as germanium (and its alloys with silicon), gallium and its alloys (in particular gallium arsenide), and other elements of group IV of the periodic table of the elements, and even compounds of III-V type, or even II-VII. A certain number of these components are semiconductors, which explains why they are used in the microelectronics field.
The formation of such microelectronics components often involves a step during which a layer of silicon on insulator, abbreviated to SOI, is formed, that is to say a useful layer of monocrystalline silicon on an insulating layer which defines one of the faces of the layer; since the microelectronics field has opened up to materials other than silicon, the expression SOI has continued to be used even when the useful layer is of a material different from silicon. Below, numerous explanations are given in the case of silicon, but it is to be understood that they can be generalized to other materials in the microelectronics field.
There are several methods for manufacturing an SOI type layer.
Thus, it is known to thermally oxidize a wafer of silicon (generally monocrystalline silicon) in order to transform it wholly or partly into silicon oxide. This first wafer is then bonded, in particular by molecular bonding, to a second wafer of silicon (generally of monocrystalline silicon); it then suffices to make one or other of the wafers thinner to obtain a layer of silicon on a layer of silicon oxide. This thinning is generally carried out by means of grinding followed by chemical mechanical polishing. Such a technique enables a layer of silicon to be obtained with a wide range of thicknesses; in particular it is thereby possible to obtain layers as thick as desired; however, it proves to be difficult to obtain a good level of homogeneity of thickness (typically a thickness only varies +/− 10% relative to the average value) below the order of 5 microns thickness, it being recalled that a wafer, in the microelectronics field, is typically a disk the diameter of which is of the order of 200 to 300 nm, or even greater.
When it is desired to obtain thinner films of silicon for which the thickness is well controlled, it is known to use a technique known under the name “Smart Cut”™ which, in a simplified version, consists in implanting a silicon wafer oxidized at the surface (with a thermal oxide layer of silicon which typically has a thickness of approximately 145 nm) with hydrogen ions, in bonding that wafer, for example by molecular bonding, onto another silicon wafer, then of inducing separation within the assembly so obtained, at the implantation peak, for example using thermal annealing, so as to obtain a thin film of silicon on a layer of silicon oxide (i.e. the part of the original wafer situated between the implantation face and the location of the implantation peak). An important advantage of this technique is that the original wafer, after separation of that thin film joined to the oxide layer, may be recycled for the formation of other thin films, which is very worthwhile in terms of cost relative to the preceding technique which involves consuming the entire substrate apart from the desired layers. With this “Smart Cut”™ technique, small thicknesses may be obtained, between a few nanometers and a few microns with a very good level of homogeneity (typically at most equal to 1%). However, this technique is poorly adapted for obtaining layers of more than 3 microns, since the thickness of the hybrid layer which is separated corresponds to the depth of implantation; it can be understood that there are limits to this thickness, given that implantations of ions are generally carried out at 200 KeV at most (which for silicon corresponds to an implantation peak at around 2.5 μm). It is of course possible to make up the layer so obtained by growth of the thin film by epitaxy until the desired thickness is reached, but the overall cost then becomes greater than that of the first technique cited above.
Another technique to obtain layers of SOI type is known under the name “Eltran”®, which consists in producing, in a silicon wafer, a layer of porous silicon, then in growing a film of monocrystalline silicon by epitaxy on that porous film. The surface of this film is next oxidized thermally, then bonded, for example by molecular bonding, onto a second silicon wafer, then a fracture is induced within the porous layer so as to transfer the monocrystalline silicon film onto that second wafer. It can be understood that, like the “Smart Cut” ™ technique, this technique enables very thin layers to be obtained with a good level of homogeneity, as well as the recycling of the part of the original wafer from which the thin film separated. However, this technique is relatively expensive, given the cost of the steps of forming porosity and epitaxy, such that this technique is in practice usable only for thicknesses below a few microns.
Thus the three aforesaid techniques each have limitations. The first only enables thick films to be formed (5 microns and beyond, in practice) while having a high cost due to the consumption of the unused part of the wafers employed, whereas the following two techniques consume less material, but implement relatively expensive steps; furthermore they are limited to small thicknesses (3 microns and below).